1. Field of the Invention
This invention is related to the field of processor arithmetic units and, more particularly, to leading one prediction in floating point arithmetic units.
2. Description of the Related Art
Floating point arithmetic is a common feature of modern instruction set architectures. Generally, floating point numbers are represented with a value including a sign bit (s), a biased exponent (exp), and a significand (sd). The floating point number being represented is equal to (−1)s*2exp-bias*1.sd (assuming the number is normalized). The value of the bias may depend on the precision of the floating point number, as may the number of bits in the exponent and the significand. For example, the Institute of Electrical and Electronic Engineers (IEEE) has promulgated standards (e.g. IEEE 754) for floating point numbers including single precision (32 bit) and double precision (64 bit) numbers. The single precision number includes 1 sign bit, 8 bits of exponent, and 23 bits of significand. The double precision number includes 1 sign bit, 11 bits of exponent, and 52 bits of significand. In both cases, the digit to the left of the binary point is implied and thus not represented in the 23 or 52 bit significand. If the number is normalized (or simply “normal”), the implied bit is a binary one. If the number is denormalized (or simply “denorm”), the implied bit is a binary zero (and the exponent has a predetermined value indicating that the number is a denorm). Denormal numbers are frequently used to represent numbers which cannot be represented with both an implied bit of one and an exponent within the range provided for the given precision.
When adding or subtracting floating point numbers, the numbers are generally adjusted until the exponents are equal. Specifically, the significand of the number with the smaller exponent may be right shifted until the exponents of the numbers are equal (thus, the implied bit of the adjusted number is zero and the adjusted number is a denorm) and the number with the larger exponent is held constant. The significands of the adjusted numbers can be added/subtracted, and the resulting significand with the larger exponent represents the resulting floating point number.
If the magnitudes of the numbers are similar, the subtraction of the significands (or the addition, if the sign bits are opposite) may yield a resulting significand having one or more zeros in the most significant bits before the first one is detected (leading zeros). For example (using eight bit significands for convenience, with the significands illustrated in binary with the most significant bit first), 1011 1000−1011 0000=0000 1000. In this example, there are four leading zeros before the first one (the leading one) in the resulting significand. Such a result requires modification to represent the result in normal form. Particularly, the resulting significand should be left shifted until the most significant bit is a one and the exponent of the result should be adjusted accordingly.
Unfortunately, the normalization of the result is time consuming. Generally, the leading zeros are counted to produce a shift amount, and the resulting significand is left shifted by the shift amount (and the exponent of the result is the larger exponent of the numbers being added decreased by the shift amount). The serial process of generating the resulting significand, counting the leading zeros, and left shifting is time consuming, and thus increases the latency for completing the addition/subtraction.
Some floating point execution units including a leading one predictor which operates concurrent with the adder. The leading one predictor predicts the position within the result of the leading one, and the prediction is either correct or errors by one bit to the more significant side of the actual leading one. The resulting significand is shifted by a shift amount corresponding to the leading one prediction. The most significant bit of the shifted result is then analyzed to determine if the leading one prediction is correct. If the most significant bit of the shifted result is a one, the leading one prediction is correct. If the most significant bit is a zero, the second most significant bit will be a one and the shifted result is shifted by one more bit to complete the normalization. Unfortunately, analyzing the most significant bit resulting from the shift still adds latency to the addition.
Some other methods attempt to alleviate the delay of analyzing the most significant bit by, concurrent with the addition and leading one prediction, generating a correction of the prediction for cases in which the prediction is incorrect. For example, such a method is proposed in “Leading One Prediction with Concurrent Position Correction” by J. D. Bruguera and T. Lang in IEEE Transactions on Computers, Vol. 48, No. 10, October 1999 (incorporated herein by reference in its entirety). Unfortunately, such methods may increase the area occupied by the prediction logic by approximately 50%.